| Property | Value |
| Project Name: | h:\skola\apc\semestralka\cpu\_ise |
| Target Device: | xc2s200e |
| Report Generated: | Thursday 12/14/06 at 18:45 |
| Printable Summary (View as HTML) | cpu_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slices: | 169 | 2352 | 7% | |
| Number of Slice Flip Flops: | 130 | 4704 | 2% | |
| Number of 4 input LUTs: | 257 | 4704 | 5% | |
| Number of bonded IOBs: | 72 | 146 | 49% | |
| Number of BRAMs: | 10 | 14 | 71% | |
| Number of GCLKs: | 1 | 4 | 25% |
| Property | Value |
| Data Not Yet Available |
| Constraint(s) | Requested | Actual | Logic Levels |
| Data Not Yet Available |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Thursday 12/14/06 at 18:45 |
| Translation Report | Out-of-Date | Thursday 12/14/06 at 18:36 |
| Map Report | Out-of-Date | Thursday 12/14/06 at 18:36 |
| Pad Report | Out-of-Date | Thursday 12/14/06 at 18:37 |
| Place and Route Report | Out-of-Date | Thursday 12/14/06 at 18:37 |
| Post Place and Route Static Timing Report | Out-of-Date | Thursday 12/14/06 at 18:37 |