# Reading C:/Modeltech_6.1a/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.1a Jul 19 2005 
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do cpu_tb_vhd.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling entity kcpsm3
# -- Compiling architecture low_level_definition of kcpsm3
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling entity app_rom
# -- Compiling architecture low_level_definition of app_rom
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling entity sped_rom
# -- Compiling architecture low_level_definition of sped_rom
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity cpu
# -- Compiling architecture cpu_body of cpu
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity cpu_tb_vhd
# -- Compiling architecture behavior of cpu_tb_vhd
# vsim -lib work -t 1ps cpu_tb_vhd 
# Loading C:\Modeltech_6.1a\win32/../std.standard
# Loading C:\Modeltech_6.1a\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.numeric_std(body)
# Loading work.cpu_tb_vhd(behavior)
# Loading work.cpu(cpu_body)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.vcomponents
# Loading work.kcpsm3(low_level_definition)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.lut1(lut1_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fdr(fdr_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fds(fds_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.lut4(lut4_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fd(fd_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.lut3(lut3_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.lut2(lut2_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.muxcy(muxcy_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.xorcy(xorcy_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.inv(inv_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fdrse(fdrse_v)
# Loading C:\Modeltech_6.1a\win32/../std.textio(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.vital_timing(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.vital_primitives(body)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.vpkg(body)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.ram16x1d(ram16x1d_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.ram64x1s(ram64x1s_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.muxf5(muxf5_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.ram32x1s(ram32x1s_v)
# Loading work.app_rom(low_level_definition)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.ramb4_s4(ramb4_s4_v)
# Loading work.sped_rom(low_level_definition)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 450 ns  Iteration: 0  Instance: /cpu_tb_vhd/uut
do cpu_tb_vhd.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling entity kcpsm3
# -- Compiling architecture low_level_definition of kcpsm3
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling entity app_rom
# -- Compiling architecture low_level_definition of app_rom
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling entity sped_rom
# -- Compiling architecture low_level_definition of sped_rom
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity cpu
# -- Compiling architecture cpu_body of cpu
# Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity cpu_tb_vhd
# -- Compiling architecture behavior of cpu_tb_vhd
# vsim -lib work -t 1ps cpu_tb_vhd 
# Loading C:\Modeltech_6.1a\win32/../std.standard
# Loading C:\Modeltech_6.1a\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.numeric_std(body)
# Loading work.cpu_tb_vhd(behavior)
# Loading work.cpu(cpu_body)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.vcomponents
# Loading work.kcpsm3(low_level_definition)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.lut1(lut1_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fdr(fdr_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fds(fds_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.lut4(lut4_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fd(fd_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fde(fde_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.lut3(lut3_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fdre(fdre_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.lut2(lut2_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.muxcy(muxcy_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.xorcy(xorcy_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.inv(inv_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.fdrse(fdrse_v)
# Loading C:\Modeltech_6.1a\win32/../std.textio(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.vital_timing(body)
# Loading C:\Modeltech_6.1a\win32/../ieee.vital_primitives(body)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.vpkg(body)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.ram16x1d(ram16x1d_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.ram32x1s(ram32x1s_v)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.muxf5(muxf5_v)
# Loading work.app_rom(low_level_definition)
# Loading C:\Modeltech_6.1a\win32/../xilinx/vhdl/unisim.ramb4_s4(ramb4_s4_v)
# Loading work.sped_rom(low_level_definition)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run 10 us
restart -f
run 10 us
