| Property | Value |
| Project Name: | h:\skola\apc\semestralka\cpu\hwtest-sram-com\_ise |
| Target Device: | xc2s200e |
| Report Generated: | Thursday 01/04/07 at 14:54 |
| Printable Summary (View as HTML) | cpu_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops: | 82 | 4,704 | 1% | |
| Number of 4 input LUTs: | 188 | 4,704 | 3% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 139 | 2,352 | 5% | |
| Number of Slices containing only related logic: | 139 | 139 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 139 | 0% | |
| Total Number 4 input LUTs: | 257 | 4,704 | 5% | |
| Number used as logic: | 188 | |||
| Number used as a route-thru: | 1 | |||
| Number used for Dual Port RAMs: | 16 | |||
| Number used for 32x1 RAMs: | 52 | |||
| Number of bonded IOBs: | 72 | 142 | 50% | |
| Number of Block RAMs: | 10 | 14 | 71% | |
| Number of GCLKs: | 2 | 4 | 50% | |
| Number of DLLs: | 1 | 4 | 25% | |
| Number of DLL IOBs: | 1 | 4 | 25% |
| Property | Value |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| No Constraints Found |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Thursday 01/04/07 at 14:54 |
| Translation Report | Current | Thursday 01/04/07 at 14:54 |
| Map Report | Current | Thursday 01/04/07 at 14:54 |
| Pad Report | Current | Thursday 01/04/07 at 14:54 |
| Place and Route Report | Current | Thursday 01/04/07 at 14:54 |
| Post Place and Route Static Timing Report | Current | Thursday 01/04/07 at 14:54 |